1. Field
The present invention relates to a cache memory system, a data processing apparatus, and a storage apparatus, and method thereof.
2. Description of the Related Art
In a data processing apparatus, since an access latency from a processor to a main storage apparatus includes many stall cycles, a cache memory which can be accessed speedily by the processor is often provided in order to reduce the penalty associated with access from the processor to the main storage apparatus. However, when a command associated with access to a storage area where no copy of data of the main storage apparatus exists in the cache memory is executed by the processor, a cache miss hit occurs. At that time, when a load command is executed or a store command is executed in the cache memory having a write-allocating system, since an operation (move-in operation) for preparing a copy of data of the main storage apparatus in the cache memory is required, a penalty for executing a command of the processor will be caused to a certain degree.
Although occurrence frequency of the cache miss hit can be reduced by increasing capacity of the cache memory, it is not easy to increase capacity of a memory which can be accessed speedily by the processor due to trade-off between operating frequency and cost. Therefore, a method is often used for reducing the penalty associated with occurrence of the cache miss hit by providing a primary cache memory which can be accessed in the same operating speed as that of the processor and a high-capacity secondary cache memory which cannot be accessed in the same operating speed as that of the processor but can be accessed more speedily than the main storage apparatus (that is, by providing a hierarchical structure in the cache memory). In the case where a hierarchical cache memory is used in a data processing apparatus having a multi-processor structure, a storage hierarchy which is closer to the main storage apparatus is often shared among a plurality of processors. In this case, a cache control apparatus for assuring coherency of data among the plurality of processors may be provided.
Further, when data of the corresponding entry of the cache memory is rewritten by a store command (writing store data), data transferred to the cache memory by the move-in operation is never referred to by the processor. Therefore, the move-in operation has been performed uselessly and it may cause problems in processing performance and power consumption of the data processing apparatus.
In addition, techniques related to the cache memory are disclosed in, for example, Japanese Patent No. 2552704, Japanese Patent No. 3055908, and Japanese Patent No. 2637320.